{
  "name": "Circuit minimization",
  "version": "1.0.0",
  "area": {
    "name": "Circuit minimization",
    "slug": "circuits",
    "group": "Optimization",
    "kind": "circuits",
    "summary": "A working circuit proves an upper bound. Minimality additionally requires ruling out every smaller circuit in the stated gate model.",
    "definitions": [
      {
        "term": "Gate basis",
        "definition": "The allowed primitive Boolean operations; this family uses two-input NAND."
      },
      {
        "term": "Truth-table signature",
        "definition": "The complete output function over the four input rows 00, 01, 10, 11."
      },
      {
        "term": "Cost model",
        "definition": "Gate count, with acyclic wiring, reusable signals, and unrestricted fan-out."
      }
    ],
    "methodology": [
      "Evaluate the witness circuit in topological signal order.",
      "Compare its complete truth table with the target function.",
      "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
      "Reject minimality if any smaller circuit implements the target."
    ],
    "complexity": "The circuit search grows rapidly with gate count. This family keeps two inputs and at most four witness gates.",
    "common_error": "Gate-count minimality does not imply minimum delay, energy, area, or transistor count.",
    "next_question": "Add independently checked lower bounds and additional gate libraries.",
    "references": [
      "https://ocw.mit.edu/courses/6-006-introduction-to-algorithms-fall-2011/"
    ]
  },
  "records": [
    {
      "id": "KL-FCS-009",
      "version": "1.0.0",
      "domain": "Circuit minimization",
      "kind": "circuits",
      "title": "XOR with a minimum NAND count",
      "problem": "Find the fewest two-input NAND gates for XOR(a,b), with acyclic wiring, reusable signals, unrestricted fan-out, no constants, and one gate-output signal.",
      "specification": {
        "truth_table": 6,
        "row_order": "00, 01, 10, 11; row i is bit i",
        "gate_basis": "two-input NAND; repeated inputs permitted; no constants"
      },
      "claim": {
        "minimum_gates": 4
      },
      "witness": {
        "gates": [
          [
            0,
            1
          ],
          [
            0,
            2
          ],
          [
            1,
            2
          ],
          [
            3,
            4
          ]
        ]
      },
      "verification_scope": "Witness truth table + complete smaller-circuit search",
      "explanation": "The four-gate witness yields the XOR truth table. The checker enumerates every topologically ordered circuit with fewer than four gates, identifying symmetric NAND inputs, and finds none that implements XOR.",
      "limitations": "Minimality is relative to this precise gate basis and wiring model. It says nothing about transistor count, delay, power, or other gate libraries.",
      "verification_status": "mechanically-checked",
      "review_status": "awaiting-independent-review",
      "provenance": {
        "origin": "Original Kenton Labs reference instance, authored with Codex assistance on 2026-10-11.",
        "external_dataset": null,
        "model_run": null
      },
      "references": [
        "https://ocw.mit.edu/courses/6-006-introduction-to-algorithms-fall-2011/"
      ],
      "license_status": "not-yet-selected",
      "dataset": {
        "family": "circuits",
        "task": "Find the fewest two-input NAND gates for XOR(a,b), with acyclic wiring, reusable signals, unrestricted fan-out, no constants, and one gate-output signal.",
        "input_encoding": "Structured JSON; field meanings are stated in the specification.",
        "coverage": "Witness truth table + complete smaller-circuit search",
        "acceptance": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "generation": "Deterministic finite fixture; full enumeration or witness replay as stated.",
        "split_policy": "Reference corpus for exposition and reproduction; no train/test evaluation split is claimed."
      },
      "lesson": {
        "motivation": "A working circuit proves an upper bound. Minimality additionally requires ruling out every smaller circuit in the stated gate model.",
        "definitions": [
          {
            "term": "Gate basis",
            "definition": "The allowed primitive Boolean operations; this family uses two-input NAND."
          },
          {
            "term": "Truth-table signature",
            "definition": "The complete output function over the four input rows 00, 01, 10, 11."
          },
          {
            "term": "Cost model",
            "definition": "Gate count, with acyclic wiring, reusable signals, and unrestricted fan-out."
          }
        ],
        "reasoning": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "worked_example": "The four-gate witness yields the XOR truth table. The checker enumerates every topologically ordered circuit with fewer than four gates, identifying symmetric NAND inputs, and finds none that implements XOR.",
        "complexity": "The circuit search grows rapidly with gate count. This family keeps two inputs and at most four witness gates.",
        "common_error": "Gate-count minimality does not imply minimum delay, energy, area, or transistor count.",
        "further_work": "Add independently checked lower bounds and additional gate libraries."
      },
      "related_ids": [
        "KL-FCS-022",
        "KL-FCS-023"
      ]
    },
    {
      "id": "KL-FCS-022",
      "version": "1.0.0",
      "domain": "Circuit minimization",
      "kind": "circuits",
      "title": "Negation from a repeated NAND input",
      "problem": "Minimize the gate count for the declared two-input truth-table signature.",
      "specification": {
        "truth_table": 3,
        "row_order": "00, 01, 10, 11; row i is bit i",
        "gate_basis": "two-input NAND; repeated inputs allowed; no constants"
      },
      "claim": {
        "minimum_gates": 1
      },
      "witness": {
        "gates": [
          [
            0,
            0
          ]
        ]
      },
      "verification_scope": "Complete truth table + zero-gate lower bound",
      "explanation": "A single NAND gate supplies the target. Neither available input wire has the same signature, so no zero-gate implementation exists.",
      "limitations": "The lower bound applies only to the specified two-input NAND basis.",
      "verification_status": "mechanically-checked",
      "review_status": "awaiting-independent-review",
      "provenance": {
        "origin": "Original Kenton Labs reference instance, authored with Codex assistance on 2026-10-11.",
        "external_dataset": null,
        "model_run": null
      },
      "references": [
        "https://ocw.mit.edu/courses/6-006-introduction-to-algorithms-fall-2011/"
      ],
      "license_status": "not-yet-selected",
      "dataset": {
        "family": "circuits",
        "task": "Minimize the gate count for the declared two-input truth-table signature.",
        "input_encoding": "Structured JSON; field meanings are stated in the specification.",
        "coverage": "Complete truth table + zero-gate lower bound",
        "acceptance": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "generation": "Deterministic finite fixture; full enumeration or witness replay as stated.",
        "split_policy": "Reference corpus for exposition and reproduction; no train/test evaluation split is claimed."
      },
      "lesson": {
        "motivation": "A working circuit proves an upper bound. Minimality additionally requires ruling out every smaller circuit in the stated gate model.",
        "definitions": [
          {
            "term": "Gate basis",
            "definition": "The allowed primitive Boolean operations; this family uses two-input NAND."
          },
          {
            "term": "Truth-table signature",
            "definition": "The complete output function over the four input rows 00, 01, 10, 11."
          },
          {
            "term": "Cost model",
            "definition": "Gate count, with acyclic wiring, reusable signals, and unrestricted fan-out."
          }
        ],
        "reasoning": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "worked_example": "A single NAND gate supplies the target. Neither available input wire has the same signature, so no zero-gate implementation exists.",
        "complexity": "The circuit search grows rapidly with gate count. This family keeps two inputs and at most four witness gates.",
        "common_error": "Gate-count minimality does not imply minimum delay, energy, area, or transistor count.",
        "further_work": "Add independently checked lower bounds and additional gate libraries."
      },
      "related_ids": [
        "KL-FCS-009",
        "KL-FCS-023"
      ]
    },
    {
      "id": "KL-FCS-023",
      "version": "1.0.0",
      "domain": "Circuit minimization",
      "kind": "circuits",
      "title": "The NAND primitive is minimal",
      "problem": "Minimize the gate count for the declared two-input truth-table signature.",
      "specification": {
        "truth_table": 7,
        "row_order": "00, 01, 10, 11; row i is bit i",
        "gate_basis": "two-input NAND; repeated inputs allowed; no constants"
      },
      "claim": {
        "minimum_gates": 1
      },
      "witness": {
        "gates": [
          [
            0,
            1
          ]
        ]
      },
      "verification_scope": "Complete truth table + zero-gate lower bound",
      "explanation": "A single NAND gate supplies the target. Neither available input wire has the same signature, so no zero-gate implementation exists.",
      "limitations": "The lower bound applies only to the specified two-input NAND basis.",
      "verification_status": "mechanically-checked",
      "review_status": "awaiting-independent-review",
      "provenance": {
        "origin": "Original Kenton Labs reference instance, authored with Codex assistance on 2026-10-11.",
        "external_dataset": null,
        "model_run": null
      },
      "references": [
        "https://ocw.mit.edu/courses/6-006-introduction-to-algorithms-fall-2011/"
      ],
      "license_status": "not-yet-selected",
      "dataset": {
        "family": "circuits",
        "task": "Minimize the gate count for the declared two-input truth-table signature.",
        "input_encoding": "Structured JSON; field meanings are stated in the specification.",
        "coverage": "Complete truth table + zero-gate lower bound",
        "acceptance": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "generation": "Deterministic finite fixture; full enumeration or witness replay as stated.",
        "split_policy": "Reference corpus for exposition and reproduction; no train/test evaluation split is claimed."
      },
      "lesson": {
        "motivation": "A working circuit proves an upper bound. Minimality additionally requires ruling out every smaller circuit in the stated gate model.",
        "definitions": [
          {
            "term": "Gate basis",
            "definition": "The allowed primitive Boolean operations; this family uses two-input NAND."
          },
          {
            "term": "Truth-table signature",
            "definition": "The complete output function over the four input rows 00, 01, 10, 11."
          },
          {
            "term": "Cost model",
            "definition": "Gate count, with acyclic wiring, reusable signals, and unrestricted fan-out."
          }
        ],
        "reasoning": [
          "Evaluate the witness circuit in topological signal order.",
          "Compare its complete truth table with the target function.",
          "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
          "Reject minimality if any smaller circuit implements the target."
        ],
        "worked_example": "A single NAND gate supplies the target. Neither available input wire has the same signature, so no zero-gate implementation exists.",
        "complexity": "The circuit search grows rapidly with gate count. This family keeps two inputs and at most four witness gates.",
        "common_error": "Gate-count minimality does not imply minimum delay, energy, area, or transistor count.",
        "further_work": "Add independently checked lower bounds and additional gate libraries."
      },
      "related_ids": [
        "KL-FCS-009",
        "KL-FCS-022"
      ]
    }
  ],
  "verification": [
    {
      "id": "KL-FCS-009",
      "status": "mechanically-checked",
      "check_units": 4,
      "scope": "Witness truth table + complete smaller-circuit search",
      "review_status": "awaiting-independent-review"
    },
    {
      "id": "KL-FCS-022",
      "status": "mechanically-checked",
      "check_units": 1,
      "scope": "Complete truth table + zero-gate lower bound",
      "review_status": "awaiting-independent-review"
    },
    {
      "id": "KL-FCS-023",
      "status": "mechanically-checked",
      "check_units": 1,
      "scope": "Complete truth table + zero-gate lower bound",
      "review_status": "awaiting-independent-review"
    }
  ]
}