# XOR with a minimum NAND count

KL-FCS-009 · Circuit minimization · version 1.0.0

## Problem

Find the fewest two-input NAND gates for XOR(a,b), with acyclic wiring, reusable signals, unrestricted fan-out, no constants, and one gate-output signal.

## Context

A working circuit proves an upper bound. Minimality additionally requires ruling out every smaller circuit in the stated gate model.

## Definitions

- **Gate basis**: The allowed primitive Boolean operations; this family uses two-input NAND.
- **Truth-table signature**: The complete output function over the four input rows 00, 01, 10, 11.
- **Cost model**: Gate count, with acyclic wiring, reusable signals, and unrestricted fan-out.

## Checked result

Minimum gates: 4.

The four-gate witness yields the XOR truth table. The checker enumerates every topologically ordered circuit with fewer than four gates, identifying symmetric NAND inputs, and finds none that implements XOR.

## Checker reasoning

1. Evaluate the witness circuit in topological signal order.
2. Compare its complete truth table with the target function.
3. Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.
4. Reject minimality if any smaller circuit implements the target.

## Dataset construction

{
  "family": "circuits",
  "task": "Find the fewest two-input NAND gates for XOR(a,b), with acyclic wiring, reusable signals, unrestricted fan-out, no constants, and one gate-output signal.",
  "input_encoding": "Structured JSON; field meanings are stated in the specification.",
  "coverage": "Witness truth table + complete smaller-circuit search",
  "acceptance": [
    "Evaluate the witness circuit in topological signal order.",
    "Compare its complete truth table with the target function.",
    "Enumerate all smaller acyclic circuits, identifying symmetric NAND inputs.",
    "Reject minimality if any smaller circuit implements the target."
  ],
  "generation": "Deterministic finite fixture; full enumeration or witness replay as stated.",
  "split_policy": "Reference corpus for exposition and reproduction; no train/test evaluation split is claimed."
}

## Formal payload

```json
{
  "specification": {
    "truth_table": 6,
    "row_order": "00, 01, 10, 11; row i is bit i",
    "gate_basis": "two-input NAND; repeated inputs permitted; no constants"
  },
  "claim": {
    "minimum_gates": 4
  },
  "witness": {
    "gates": [
      [
        0,
        1
      ],
      [
        0,
        2
      ],
      [
        1,
        2
      ],
      [
        3,
        4
      ]
    ]
  }
}
```

## Complexity

The circuit search grows rapidly with gate count. This family keeps two inputs and at most four witness gates.

## Limits

Minimality is relative to this precise gate basis and wiring model. It says nothing about transistor count, delay, power, or other gate libraries.

## Common error and further work

Gate-count minimality does not imply minimum delay, energy, area, or transistor count.

Add independently checked lower bounds and additional gate libraries.

## Verification

Witness truth table + complete smaller-circuit search. 4 checker units.
Replay with `python3 tools/verify.py`. Mechanical status: checked; human review
has not yet been recorded. Custom Python verification, not a proof-assistant
claim. Checker 1.0.0 and exact source hashes are in `verification.json`.

## Provenance and references

Original Kenton Labs reference instance, authored with Codex assistance on 2026-10-11.
No external dataset or model-generation experiment. Reuse-license selection
remains pending.

- [Conceptual reference](https://ocw.mit.edu/courses/6-006-introduction-to-algorithms-fall-2011/)